1. Field of the Invention
The present invention relates to a semiconductor device including a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) that uses an SOI (Silicon-On-Insulator) substrate and a method of fabricating the same.
2. Description of the Related Art
A MOSFET that uses an SOI substrate offers advantages over an ordinary bulk MOSFET. The reduction of parasitic capacitance improves circuit performance because no p-n junction exists on the bottom regions of source and drain regions. In addition, undesirable performance such as latch-up and so on, which is caused by a parasitic element, can be eliminated because an element is completely separated from adjacent elements on the SOI substrate.
There are two types of SOI, that is, a fully depleted type (hereinafter referred to as FD (Fully Depleted) type) and a partially depleted type (hereinafter referred to as PD (Partially Depleted) type). The FD type offers advantages in that since there is no depletion layer capacitance, when a voltage is applied to a gate, a precipitous channel formation can be realized, that is, precipitous sub-threshold characteristics can be realized; and a short channel effect can be largely suppressed due to the thickness of the silicon layer on a buried oxide layer (hereinafter referred to as BOX layer).
In a semiconductor device using an SOI substrate, a silicon layer is completely insulated from a substrate by the BOX layer. This causes a substrate floating effect. By the substrate floating effect, holes are generated and remain in a body region of the silicon layer when carriers (electrons in the case of NMOS) induce collision ionization in the neighborhood of a drain region. Such remaining holes increase a body voltage and cause an increase of a drain current. As a result, a breakdown voltage between source and drain regions is lowered. Additionally, such a variation of the body voltage causes undesirable performance when the current largely varies with respect to a voltage, in particular in the case of an analog circuit.
In a semiconductor device using an SOI substrate, in order to suppress the substrate floating effect, a method of fixing a body voltage is used. The method of fixing the body voltage is disclosed in, for example, Kokai (Japanese unexamined patent publication) No. 3-94471. In the method, a high concentration extracting region (a p+ layer in the case of NMOS) is in contact with a source region and an end portion of a body region in which an electrically conducting channel is formed, and the high concentration extracting region is formed along the surface of the silicon layer (SOI layer). The remaining holes are thereby extracted and the increase of the body voltage is inhibited from occurring.
According to the method described above, However, since the extracting region is necessary to be formed adjacent to the source region, a decrease in the degree of integration results. Such a decrease in the degree of integration is very disadvantageous in an LSI that is integrated with a gate width of approximately 0.2 μm. In this point, as described in Kokai No. 3-94471, it is disclosed that since the layer of the extracting region is disposed below the layer of the source and drain regions in the semiconductor device, the decrease in the degree of integration can be avoided. Technically it is possible to fabricate a PD type of SOI MOSFET having such a structure when the silicon layer which constitutes the SOI MOSFET is thick. However, there is a problem in that it is difficult to fabricate a FD type of SOI MOSFET having such a structure when the silicon layer is thick.